Mise à jour du SHIM suite à réunion KiCAD (connecteur intercalaire sur GPIO)
This commit is contained in:
Pierrick C
parent
669a31ce69
commit
5efa599b93
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@ -93,4 +93,17 @@ X GND 1 0 0 0 D 50 50 1 1 W N
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ENDDRAW
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ENDDEF
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#
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# PWR_FLAG
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#
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DEF PWR_FLAG #FLG 0 0 N N 1 F P
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F0 "#FLG" 0 95 50 H I C CNN
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F1 "PWR_FLAG" 0 180 50 H V C CNN
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F2 "" 0 0 50 H V C CNN
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F3 "" 0 0 50 H V C CNN
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DRAW
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X pwr 1 0 0 0 U 50 50 0 0 w
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P 6 0 1 0 0 0 0 50 -75 100 0 150 75 100 0 50 N
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ENDDRAW
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ENDDEF
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#
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#End Library
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@ -28,6 +28,7 @@ LIBS:opto
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LIBS:atmel
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LIBS:contrib
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LIBS:valves
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LIBS:Serial-SHIM-cache
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EELAYER 25 0
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EELAYER END
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$Descr A4 11693 8268
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@ -48,7 +49,7 @@ U 1 1 59BCE9F7
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P 7850 4800
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F 0 "Serial1" H 7850 5050 50 0000 C CNN
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F 1 "CONN_01X04" H 7950 4550 50 0000 C CNN
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F 2 "" H 7850 4800 50 0000 C CNN
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F 2 "Pin_Headers:Pin_Header_Straight_1x04" H 8450 5150 50 0000 C CNN
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F 3 "" H 7850 4800 50 0000 C CNN
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1 7850 4800
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1 0 0 -1
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@ -59,14 +60,11 @@ U 1 1 59BCEAE4
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P 6750 4850
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F 0 "PI-GPIO1" H 6750 5150 50 0000 C CNN
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F 1 "CONN_02X05" H 6750 4550 50 0000 C CNN
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F 2 "" H 6750 3650 50 0000 C CNN
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F 2 "Pin_Headers:Pin_Header_Straight_2x05" H 6200 5250 50 0000 C CNN
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F 3 "" H 6750 3650 50 0000 C CNN
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1 6750 4850
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1 0 0 -1
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$EndComp
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Wire Wire Line
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7000 4650 7650 4650
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Connection ~ 7150 4650
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Wire Wire Line
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7000 4850 7550 4850
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Wire Wire Line
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@ -83,10 +81,6 @@ Wire Wire Line
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7000 5050 7650 5050
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Wire Wire Line
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7650 5050 7650 4950
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Wire Wire Line
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7000 4750 7150 4750
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Wire Wire Line
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7150 4750 7150 4650
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$Comp
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L GND #PWR01
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U 1 1 59BCEDDF
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@ -100,47 +94,67 @@ F 3 "" H 7300 4850 50 0000 C CNN
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$EndComp
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$Comp
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L +5V #PWR02
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U 1 1 59BCEDF7
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P 7150 4650
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F 0 "#PWR02" H 7150 4500 50 0001 C CNN
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F 1 "+5V" H 7150 4790 50 0000 C CNN
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F 2 "" H 7150 4650 50 0000 C CNN
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F 3 "" H 7150 4650 50 0000 C CNN
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1 7150 4650
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U 1 1 59BCF0FF
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P 7900 4000
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F 0 "#PWR02" H 7900 3850 50 0001 C CNN
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F 1 "+5V" H 7900 4140 50 0000 C CNN
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F 2 "" H 7900 4000 50 0000 C CNN
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F 3 "" H 7900 4000 50 0000 C CNN
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1 7900 4000
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-1 0 0 1
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$EndComp
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$Comp
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L GND #PWR03
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U 1 1 59BCF11C
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P 8300 4000
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F 0 "#PWR03" H 8300 3750 50 0001 C CNN
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F 1 "GND" H 8300 3850 50 0000 C CNN
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F 2 "" H 8300 4000 50 0000 C CNN
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F 3 "" H 8300 4000 50 0000 C CNN
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1 8300 4000
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1 0 0 -1
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$EndComp
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Wire Wire Line
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7000 4500 7000 4750
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Connection ~ 7000 4650
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Wire Wire Line
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7000 4650 7650 4650
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NoConn ~ 6500 4650
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NoConn ~ 6500 4750
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NoConn ~ 6500 4850
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NoConn ~ 6500 4950
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NoConn ~ 6500 5050
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$Comp
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L PWR_FLAG #FLG04
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U 1 1 59C3E871
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P 7900 4000
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F 0 "#FLG04" H 7900 4095 50 0001 C CNN
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F 1 "PWR_FLAG" H 7900 4180 50 0000 C CNN
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F 2 "" H 7900 4000 50 0000 C CNN
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F 3 "" H 7900 4000 50 0000 C CNN
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1 7900 4000
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1 0 0 -1
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$EndComp
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$Comp
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L +3.3V #PWR?
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U 1 1 59BCEE96
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P 6500 4650
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F 0 "#PWR?" H 6500 4500 50 0001 C CNN
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F 1 "+3.3V" V 6500 4900 50 0000 C CNN
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F 2 "" H 6500 4650 50 0000 C CNN
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F 3 "" H 6500 4650 50 0000 C CNN
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1 6500 4650
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0 -1 -1 0
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L PWR_FLAG #FLG05
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U 1 1 59C3E889
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P 8300 4000
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F 0 "#FLG05" H 8300 4095 50 0001 C CNN
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F 1 "PWR_FLAG" H 8300 4180 50 0000 C CNN
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F 2 "" H 8300 4000 50 0000 C CNN
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F 3 "" H 8300 4000 50 0000 C CNN
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1 8300 4000
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1 0 0 -1
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$EndComp
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Wire Wire Line
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6200 4750 6500 4750
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Text GLabel 6200 4750 0 60 Input ~ 0
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SDA
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Text GLabel 6450 4850 0 60 Input ~ 0
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SDC
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Text GLabel 6200 4950 0 60 Input ~ 0
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GPCLK0
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Wire Wire Line
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6200 4950 6500 4950
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Wire Wire Line
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6450 4850 6500 4850
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$Comp
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L GND #PWR?
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U 1 1 59BCF041
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P 6500 5050
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F 0 "#PWR?" H 6500 4800 50 0001 C CNN
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F 1 "GND" V 6500 4850 50 0000 C CNN
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F 2 "" H 6500 5050 50 0000 C CNN
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F 3 "" H 6500 5050 50 0000 C CNN
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1 6500 5050
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0 1 1 0
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L +5V #PWR06
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U 1 1 59C3E8A7
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P 7000 4500
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F 0 "#PWR06" H 7000 4350 50 0001 C CNN
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F 1 "+5V" H 7000 4640 50 0000 C CNN
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F 2 "" H 7000 4500 50 0000 C CNN
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F 3 "" H 7000 4500 50 0000 C CNN
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1 7000 4500
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1 0 0 -1
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$EndComp
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$EndSCHEMATC
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@ -2,17 +2,21 @@
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(general
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(links 5)
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(no_connects 0)
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(no_connects 1)
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(area 0 0 0 0)
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(thickness 1.6)
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(drawings 0)
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(tracks 15)
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(drawings 4)
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(tracks 14)
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(zones 0)
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(modules 2)
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(nets 10)
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)
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(page A4)
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(title_block
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(date 2017-09-21)
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)
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(layers
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(0 F.Cu signal)
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(31 B.Cu signal)
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@ -38,10 +42,10 @@
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(setup
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(last_trace_width 0.25)
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(trace_clearance 0.2)
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(trace_clearance 0.1)
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(zone_clearance 0.508)
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(zone_45_only no)
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(trace_min 0.2)
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(trace_min 0.15)
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(segment_width 0.2)
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(edge_width 0.15)
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(via_size 0.6)
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@ -61,7 +65,8 @@
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(pad_size 1.524 1.524)
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(pad_drill 0.762)
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(pad_to_mask_clearance 0.2)
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(aux_axis_origin 0 0)
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(aux_axis_origin 129.54 118.11)
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(grid_origin 129.54 118.11)
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(visible_elements FFFFFF7F)
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(pcbplotparams
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(layerselection 0x00030_80000001)
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@ -92,23 +97,22 @@
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(net 0 "")
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(net 1 "Net-(PI-GPIO1-Pad1)")
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(net 2 5V)
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(net 3 "Net-(PI-GPIO1-Pad3)")
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(net 4 "Net-(PI-GPIO1-Pad5)")
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(net 5 "Net-(PI-GPIO1-Pad6)")
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(net 6 "Net-(PI-GPIO1-Pad7)")
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(net 7 "Net-(PI-GPIO1-Pad8)")
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(net 8 "Net-(PI-GPIO1-Pad9)")
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(net 9 "Net-(PI-GPIO1-Pad10)")
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(net 2 "Net-(PI-GPIO1-Pad3)")
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(net 3 "Net-(PI-GPIO1-Pad5)")
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(net 4 "Net-(PI-GPIO1-Pad6)")
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(net 5 "Net-(PI-GPIO1-Pad7)")
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(net 6 "Net-(PI-GPIO1-Pad8)")
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(net 7 "Net-(PI-GPIO1-Pad9)")
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(net 8 "Net-(PI-GPIO1-Pad10)")
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(net 9 +5V)
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(net_class Default "This is the default net class."
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(clearance 0.2)
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(clearance 0.1)
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(trace_width 0.25)
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(via_dia 0.6)
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(via_drill 0.4)
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(uvia_dia 0.3)
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(uvia_drill 0.1)
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(add_net 5V)
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(add_net "Net-(PI-GPIO1-Pad1)")
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(add_net "Net-(PI-GPIO1-Pad10)")
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(add_net "Net-(PI-GPIO1-Pad3)")
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@ -119,15 +123,25 @@
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(add_net "Net-(PI-GPIO1-Pad9)")
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)
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(module Pin_Headers:Pin_Header_Straight_2x05 (layer F.Cu) (tedit 0) (tstamp 59BDEFF5)
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(at 158.75 102.87)
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(net_class PWR ""
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(clearance 0.15)
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(trace_width 0.4)
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(via_dia 0.6)
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(via_drill 0.4)
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(uvia_dia 0.3)
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(uvia_drill 0.1)
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(add_net +5V)
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)
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(module Pin_Headers:Pin_Header_Straight_2x05 (layer F.Cu) (tedit 59C3F72F) (tstamp 59C4A79A)
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(at 148.5011 105.0036)
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(descr "Through hole pin header")
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(tags "pin header")
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(path /59BCEAE4)
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(fp_text reference PI-GPIO1 (at 0 -5.1) (layer F.SilkS)
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(fp_text reference PI-GPIO1 (at -4.9911 10.5664) (layer F.SilkS)
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_text value CONN_02X05 (at 0 -3.1) (layer F.Fab)
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(fp_text value CONN_02X05 (at -2.4511 4.2164 90) (layer F.Fab)
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_line (start -1.75 -1.75) (end -1.75 11.95) (layer F.CrtYd) (width 0.05))
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@ -145,23 +159,23 @@
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(pad 1 thru_hole rect (at 0 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 1 "Net-(PI-GPIO1-Pad1)"))
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(pad 2 thru_hole oval (at 2.54 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 2 5V))
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(net 9 +5V))
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(pad 3 thru_hole oval (at 0 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 3 "Net-(PI-GPIO1-Pad3)"))
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(net 2 "Net-(PI-GPIO1-Pad3)"))
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(pad 4 thru_hole oval (at 2.54 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 2 5V))
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(net 9 +5V))
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(pad 5 thru_hole oval (at 0 5.08) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 4 "Net-(PI-GPIO1-Pad5)"))
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(net 3 "Net-(PI-GPIO1-Pad5)"))
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(pad 6 thru_hole oval (at 2.54 5.08) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 5 "Net-(PI-GPIO1-Pad6)"))
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(net 4 "Net-(PI-GPIO1-Pad6)"))
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(pad 7 thru_hole oval (at 0 7.62) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 6 "Net-(PI-GPIO1-Pad7)"))
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(net 5 "Net-(PI-GPIO1-Pad7)"))
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(pad 8 thru_hole oval (at 2.54 7.62) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 7 "Net-(PI-GPIO1-Pad8)"))
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(net 6 "Net-(PI-GPIO1-Pad8)"))
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(pad 9 thru_hole oval (at 0 10.16) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 8 "Net-(PI-GPIO1-Pad9)"))
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(net 7 "Net-(PI-GPIO1-Pad9)"))
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(pad 10 thru_hole oval (at 2.54 10.16) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
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(net 9 "Net-(PI-GPIO1-Pad10)"))
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(net 8 "Net-(PI-GPIO1-Pad10)"))
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(model Pin_Headers.3dshapes/Pin_Header_Straight_2x05.wrl
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(at (xyz 0.05 -0.2 0))
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(scale (xyz 1 1 1))
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@ -169,57 +183,117 @@
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)
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)
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(module Pin_Headers:Pin_Header_Straight_1x04 (layer F.Cu) (tedit 0) (tstamp 59BDF008)
|
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(at 148.5011 105.0036)
|
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(descr "Through hole pin header")
|
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(tags "pin header")
|
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(module Socket_Strips:Socket_Strip_Angled_1x04 (layer F.Cu) (tedit 59C3F728) (tstamp 59C4A7A2)
|
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(at 140.97 105.41 270)
|
||||
(descr "Through hole socket strip")
|
||||
(tags "socket strip")
|
||||
(path /59BCE9F7)
|
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(fp_text reference Serial1 (at 0 -5.1) (layer F.SilkS)
|
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(fp_text reference Serial1 (at 10.16 7.62 360) (layer F.SilkS)
|
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(effects (font (size 1 1) (thickness 0.15)))
|
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)
|
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(fp_text value CONN_01X04 (at 0 -3.1) (layer F.Fab)
|
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(fp_text value CONN_01X04 (at 3.81 -2.54 270) (layer F.Fab)
|
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(effects (font (size 1 1) (thickness 0.15)))
|
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)
|
||||
(fp_line (start -1.75 -1.75) (end -1.75 9.4) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 1.75 -1.75) (end 1.75 9.4) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.75 -1.75) (end 1.75 -1.75) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.75 9.4) (end 1.75 9.4) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.27 1.27) (end -1.27 8.89) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 1.27 1.27) (end 1.27 8.89) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 1.55 -1.55) (end 1.55 0) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -1.27 8.89) (end 1.27 8.89) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -1.55 0) (end -1.55 -1.55) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -1.55 -1.55) (end 1.55 -1.55) (layer F.SilkS) (width 0.15))
|
||||
(pad 1 thru_hole rect (at 0 0) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 2 5V))
|
||||
(pad 2 thru_hole oval (at 0 2.54) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 5 "Net-(PI-GPIO1-Pad6)"))
|
||||
(pad 3 thru_hole oval (at 0 5.08) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 7 "Net-(PI-GPIO1-Pad8)"))
|
||||
(pad 4 thru_hole oval (at 0 7.62) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 9 "Net-(PI-GPIO1-Pad10)"))
|
||||
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x04.wrl
|
||||
(at (xyz 0 -0.15 0))
|
||||
(fp_line (start -1.75 -1.5) (end -1.75 10.6) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 9.4 -1.5) (end 9.4 10.6) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.75 -1.5) (end 9.4 -1.5) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.75 10.6) (end 9.4 10.6) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 8.89 10.1) (end 8.89 1.27) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 6.35 10.1) (end 8.89 10.1) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 6.35 1.27) (end 8.89 1.27) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 3.81 1.27) (end 6.35 1.27) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 3.81 10.1) (end 6.35 10.1) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 6.35 10.1) (end 6.35 1.27) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 3.81 10.1) (end 3.81 1.27) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 1.27 10.1) (end 3.81 10.1) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 1.27 1.27) (end 1.27 10.1) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 1.27 1.27) (end 3.81 1.27) (layer F.SilkS) (width 0.15))
|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
|
||||
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|
||||
(connect_pads (clearance 0.508))
|
||||
(min_thickness 0.254)
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||||
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||||
|
|
|
|||
|
|
@ -1 +1,213 @@
|
|||
(kicad_pcb (version 4) (host kicad "dummy file") )
|
||||
(kicad_pcb (version 4) (host pcbnew 4.0.2+dfsg1-stable)
|
||||
|
||||
(general
|
||||
(links 5)
|
||||
(no_connects 5)
|
||||
(area 0 0 0 0)
|
||||
(thickness 1.6)
|
||||
(drawings 0)
|
||||
(tracks 0)
|
||||
(zones 0)
|
||||
(modules 2)
|
||||
(nets 10)
|
||||
)
|
||||
|
||||
(page A4)
|
||||
(title_block
|
||||
(date 2017-09-21)
|
||||
)
|
||||
|
||||
(layers
|
||||
(0 F.Cu signal)
|
||||
(31 B.Cu signal)
|
||||
(32 B.Adhes user)
|
||||
(33 F.Adhes user)
|
||||
(34 B.Paste user)
|
||||
(35 F.Paste user)
|
||||
(36 B.SilkS user)
|
||||
(37 F.SilkS user)
|
||||
(38 B.Mask user)
|
||||
(39 F.Mask user)
|
||||
(40 Dwgs.User user)
|
||||
(41 Cmts.User user)
|
||||
(42 Eco1.User user)
|
||||
(43 Eco2.User user)
|
||||
(44 Edge.Cuts user)
|
||||
(45 Margin user)
|
||||
(46 B.CrtYd user)
|
||||
(47 F.CrtYd user)
|
||||
(48 B.Fab user)
|
||||
(49 F.Fab user)
|
||||
)
|
||||
|
||||
(setup
|
||||
(last_trace_width 0.25)
|
||||
(trace_clearance 0.2)
|
||||
(zone_clearance 0.508)
|
||||
(zone_45_only no)
|
||||
(trace_min 0.2)
|
||||
(segment_width 0.2)
|
||||
(edge_width 0.15)
|
||||
(via_size 0.6)
|
||||
(via_drill 0.4)
|
||||
(via_min_size 0.4)
|
||||
(via_min_drill 0.3)
|
||||
(uvia_size 0.3)
|
||||
(uvia_drill 0.1)
|
||||
(uvias_allowed no)
|
||||
(uvia_min_size 0.2)
|
||||
(uvia_min_drill 0.1)
|
||||
(pcb_text_width 0.3)
|
||||
(pcb_text_size 1.5 1.5)
|
||||
(mod_edge_width 0.15)
|
||||
(mod_text_size 1 1)
|
||||
(mod_text_width 0.15)
|
||||
(pad_size 1.524 1.524)
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||||
(pad_drill 0.762)
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||||
(pad_to_mask_clearance 0.2)
|
||||
(aux_axis_origin 0 0)
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||||
(visible_elements FFFFFF7F)
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(pcbplotparams
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||||
(layerselection 0x00030_80000001)
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||||
(usegerberextensions false)
|
||||
(excludeedgelayer true)
|
||||
(linewidth 0.100000)
|
||||
(plotframeref false)
|
||||
(viasonmask false)
|
||||
(mode 1)
|
||||
(useauxorigin false)
|
||||
(hpglpennumber 1)
|
||||
(hpglpenspeed 20)
|
||||
(hpglpendiameter 15)
|
||||
(hpglpenoverlay 2)
|
||||
(psnegative false)
|
||||
(psa4output false)
|
||||
(plotreference true)
|
||||
(plotvalue true)
|
||||
(plotinvisibletext false)
|
||||
(padsonsilk false)
|
||||
(subtractmaskfromsilk false)
|
||||
(outputformat 1)
|
||||
(mirror false)
|
||||
(drillshape 1)
|
||||
(scaleselection 1)
|
||||
(outputdirectory ""))
|
||||
)
|
||||
|
||||
(net 0 "")
|
||||
(net 1 "Net-(PI-GPIO1-Pad1)")
|
||||
(net 2 "Net-(PI-GPIO1-Pad3)")
|
||||
(net 3 "Net-(PI-GPIO1-Pad5)")
|
||||
(net 4 "Net-(PI-GPIO1-Pad6)")
|
||||
(net 5 "Net-(PI-GPIO1-Pad7)")
|
||||
(net 6 "Net-(PI-GPIO1-Pad8)")
|
||||
(net 7 "Net-(PI-GPIO1-Pad9)")
|
||||
(net 8 "Net-(PI-GPIO1-Pad10)")
|
||||
(net 9 +5V)
|
||||
|
||||
(net_class Default "This is the default net class."
|
||||
(clearance 0.2)
|
||||
(trace_width 0.25)
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||||
(via_dia 0.6)
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||||
(via_drill 0.4)
|
||||
(uvia_dia 0.3)
|
||||
(uvia_drill 0.1)
|
||||
(add_net +5V)
|
||||
(add_net "Net-(PI-GPIO1-Pad1)")
|
||||
(add_net "Net-(PI-GPIO1-Pad10)")
|
||||
(add_net "Net-(PI-GPIO1-Pad3)")
|
||||
(add_net "Net-(PI-GPIO1-Pad5)")
|
||||
(add_net "Net-(PI-GPIO1-Pad6)")
|
||||
(add_net "Net-(PI-GPIO1-Pad7)")
|
||||
(add_net "Net-(PI-GPIO1-Pad8)")
|
||||
(add_net "Net-(PI-GPIO1-Pad9)")
|
||||
)
|
||||
|
||||
(module Pin_Headers:Pin_Header_Straight_2x05 (layer F.Cu) (tedit 59C3ECD4) (tstamp 59C3E9B3)
|
||||
(at 161.29 105.41)
|
||||
(descr "Through hole pin header")
|
||||
(tags "pin header")
|
||||
(path /59BCEAE4)
|
||||
(fp_text reference PI-GPIO1 (at 1.27 12.7) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
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||||
(fp_text value CONN_02X05 (at -2.54 5.08 90) (layer F.Fab)
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(effects (font (size 1 1) (thickness 0.15)))
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)
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(fp_line (start -1.75 -1.75) (end -1.75 11.95) (layer F.CrtYd) (width 0.05))
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(fp_line (start -1.75 -1.75) (end 4.3 -1.75) (layer F.CrtYd) (width 0.05))
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||||
(fp_line (start -1.75 11.95) (end 4.3 11.95) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 3.81 -1.27) (end 3.81 11.43) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 3.81 11.43) (end -1.27 11.43) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -1.27 11.43) (end -1.27 1.27) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 3.81 -1.27) (end 1.27 -1.27) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 0 -1.55) (end -1.55 -1.55) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -1.55 -1.55) (end -1.55 0) (layer F.SilkS) (width 0.15))
|
||||
(pad 1 thru_hole rect (at 0 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 1 "Net-(PI-GPIO1-Pad1)"))
|
||||
(pad 2 thru_hole oval (at 2.54 0) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 9 +5V))
|
||||
(pad 3 thru_hole oval (at 0 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 2 "Net-(PI-GPIO1-Pad3)"))
|
||||
(pad 4 thru_hole oval (at 2.54 2.54) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 9 +5V))
|
||||
(pad 5 thru_hole oval (at 0 5.08) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 3 "Net-(PI-GPIO1-Pad5)"))
|
||||
(pad 6 thru_hole oval (at 2.54 5.08) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 4 "Net-(PI-GPIO1-Pad6)"))
|
||||
(pad 7 thru_hole oval (at 0 7.62) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 5 "Net-(PI-GPIO1-Pad7)"))
|
||||
(pad 8 thru_hole oval (at 2.54 7.62) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 6 "Net-(PI-GPIO1-Pad8)"))
|
||||
(pad 9 thru_hole oval (at 0 10.16) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 7 "Net-(PI-GPIO1-Pad9)"))
|
||||
(pad 10 thru_hole oval (at 2.54 10.16) (size 1.7272 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 8 "Net-(PI-GPIO1-Pad10)"))
|
||||
(model Pin_Headers.3dshapes/Pin_Header_Straight_2x05.wrl
|
||||
(at (xyz 0.05 -0.2 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 90))
|
||||
)
|
||||
)
|
||||
|
||||
(module Pin_Headers:Pin_Header_Straight_1x04 (layer F.Cu) (tedit 59C3EC46) (tstamp 59C3E9C6)
|
||||
(at 152.4 105.41)
|
||||
(descr "Through hole pin header")
|
||||
(tags "pin header")
|
||||
(path /59BCE9F7)
|
||||
(fp_text reference Serial1 (at 1.27 10.16) (layer F.SilkS)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_text value CONN_01X04 (at 2.54 3.81 90) (layer F.Fab)
|
||||
(effects (font (size 1 1) (thickness 0.15)))
|
||||
)
|
||||
(fp_line (start -1.75 -1.75) (end -1.75 9.4) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start 1.75 -1.75) (end 1.75 9.4) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.75 -1.75) (end 1.75 -1.75) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.75 9.4) (end 1.75 9.4) (layer F.CrtYd) (width 0.05))
|
||||
(fp_line (start -1.27 1.27) (end -1.27 8.89) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 1.27 1.27) (end 1.27 8.89) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 1.55 -1.55) (end 1.55 0) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -1.27 8.89) (end 1.27 8.89) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -1.55 0) (end -1.55 -1.55) (layer F.SilkS) (width 0.15))
|
||||
(fp_line (start -1.55 -1.55) (end 1.55 -1.55) (layer F.SilkS) (width 0.15))
|
||||
(pad 1 thru_hole rect (at 0 0) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 9 +5V))
|
||||
(pad 2 thru_hole oval (at 0 2.54) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 4 "Net-(PI-GPIO1-Pad6)"))
|
||||
(pad 3 thru_hole oval (at 0 5.08) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 6 "Net-(PI-GPIO1-Pad8)"))
|
||||
(pad 4 thru_hole oval (at 0 7.62) (size 2.032 1.7272) (drill 1.016) (layers *.Cu *.Mask F.SilkS)
|
||||
(net 8 "Net-(PI-GPIO1-Pad10)"))
|
||||
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x04.wrl
|
||||
(at (xyz 0 -0.15 0))
|
||||
(scale (xyz 1 1 1))
|
||||
(rotate (xyz 0 0 90))
|
||||
)
|
||||
)
|
||||
|
||||
)
|
||||
|
|
|
|||
|
|
@ -1,7 +1,7 @@
|
|||
(export (version D)
|
||||
(design
|
||||
(source /home/arofarn/Make/Cameteo/Serial-SHIM/Serial-SHIM.sch)
|
||||
(date "sam. 16 sept. 2017 11:36:59 CEST")
|
||||
(date "jeu. 21 sept. 2017 19:02:46 CEST")
|
||||
(tool "Eeschema 4.0.2+dfsg1-stable")
|
||||
(sheet (number 1) (name /) (tstamps /)
|
||||
(title_block
|
||||
|
|
@ -17,7 +17,7 @@
|
|||
(components
|
||||
(comp (ref Serial1)
|
||||
(value CONN_01X04)
|
||||
(footprint Pin_Headers:Pin_Header_Straight_1x04)
|
||||
(footprint Socket_Strips:Socket_Strip_Angled_1x04)
|
||||
(libsource (lib conn) (part CONN_01X04))
|
||||
(sheetpath (names /) (tstamps /))
|
||||
(tstamp 59BCE9F7))
|
||||
|
|
@ -68,26 +68,26 @@
|
|||
(library (logical conn)
|
||||
(uri /usr/share/kicad/library/conn.lib)))
|
||||
(nets
|
||||
(net (code 1) (name "Net-(PI-GPIO1-Pad8)")
|
||||
(node (ref Serial1) (pin 3))
|
||||
(node (ref PI-GPIO1) (pin 8)))
|
||||
(net (code 2) (name "Net-(PI-GPIO1-Pad10)")
|
||||
(node (ref PI-GPIO1) (pin 10))
|
||||
(node (ref Serial1) (pin 4)))
|
||||
(net (code 4) (name 5V)
|
||||
(node (ref Serial1) (pin 1))
|
||||
(net (code 1) (name "Net-(PI-GPIO1-Pad10)")
|
||||
(node (ref Serial1) (pin 4))
|
||||
(node (ref PI-GPIO1) (pin 10)))
|
||||
(net (code 3) (name +5V)
|
||||
(node (ref PI-GPIO1) (pin 4))
|
||||
(node (ref Serial1) (pin 1))
|
||||
(node (ref PI-GPIO1) (pin 2)))
|
||||
(net (code 5) (name "Net-(PI-GPIO1-Pad6)")
|
||||
(net (code 4) (name "Net-(PI-GPIO1-Pad1)")
|
||||
(node (ref PI-GPIO1) (pin 1)))
|
||||
(net (code 5) (name "Net-(PI-GPIO1-Pad3)")
|
||||
(node (ref PI-GPIO1) (pin 3)))
|
||||
(net (code 6) (name "Net-(PI-GPIO1-Pad5)")
|
||||
(node (ref PI-GPIO1) (pin 5)))
|
||||
(net (code 7) (name "Net-(PI-GPIO1-Pad7)")
|
||||
(node (ref PI-GPIO1) (pin 7)))
|
||||
(net (code 8) (name "Net-(PI-GPIO1-Pad9)")
|
||||
(node (ref PI-GPIO1) (pin 9)))
|
||||
(net (code 9) (name "Net-(PI-GPIO1-Pad6)")
|
||||
(node (ref Serial1) (pin 2))
|
||||
(node (ref PI-GPIO1) (pin 6)))
|
||||
(net (code 6) (name "Net-(PI-GPIO1-Pad1)")
|
||||
(node (ref PI-GPIO1) (pin 1)))
|
||||
(net (code 7) (name "Net-(PI-GPIO1-Pad3)")
|
||||
(node (ref PI-GPIO1) (pin 3)))
|
||||
(net (code 8) (name "Net-(PI-GPIO1-Pad5)")
|
||||
(node (ref PI-GPIO1) (pin 5)))
|
||||
(net (code 9) (name "Net-(PI-GPIO1-Pad7)")
|
||||
(node (ref PI-GPIO1) (pin 7)))
|
||||
(net (code 10) (name "Net-(PI-GPIO1-Pad9)")
|
||||
(node (ref PI-GPIO1) (pin 9)))))
|
||||
(net (code 10) (name "Net-(PI-GPIO1-Pad8)")
|
||||
(node (ref Serial1) (pin 3))
|
||||
(node (ref PI-GPIO1) (pin 8)))))
|
||||
|
|
@ -28,6 +28,7 @@ LIBS:opto
|
|||
LIBS:atmel
|
||||
LIBS:contrib
|
||||
LIBS:valves
|
||||
LIBS:Serial-SHIM-cache
|
||||
EELAYER 25 0
|
||||
EELAYER END
|
||||
$Descr A4 11693 8268
|
||||
|
|
@ -48,7 +49,7 @@ U 1 1 59BCE9F7
|
|||
P 7850 4800
|
||||
F 0 "Serial1" H 7850 5050 50 0000 C CNN
|
||||
F 1 "CONN_01X04" H 7950 4550 50 0000 C CNN
|
||||
F 2 "Pin_Headers:Pin_Header_Straight_1x04" H 8450 5150 50 0000 C CNN
|
||||
F 2 "Socket_Strips:Socket_Strip_Angled_1x04" H 8450 5150 50 0000 C CNN
|
||||
F 3 "" H 7850 4800 50 0000 C CNN
|
||||
1 7850 4800
|
||||
1 0 0 -1
|
||||
|
|
@ -92,38 +93,68 @@ F 3 "" H 7300 4850 50 0000 C CNN
|
|||
1 0 0 1
|
||||
$EndComp
|
||||
$Comp
|
||||
L +5V #PWR03
|
||||
L +5V #PWR02
|
||||
U 1 1 59BCF0FF
|
||||
P 7800 4050
|
||||
F 0 "#PWR03" H 7800 3900 50 0001 C CNN
|
||||
F 1 "+5V" H 7800 4190 50 0000 C CNN
|
||||
F 2 "" H 7800 4050 50 0000 C CNN
|
||||
F 3 "" H 7800 4050 50 0000 C CNN
|
||||
1 7800 4050
|
||||
1 0 0 -1
|
||||
P 7900 4000
|
||||
F 0 "#PWR02" H 7900 3850 50 0001 C CNN
|
||||
F 1 "+5V" H 7900 4140 50 0000 C CNN
|
||||
F 2 "" H 7900 4000 50 0000 C CNN
|
||||
F 3 "" H 7900 4000 50 0000 C CNN
|
||||
1 7900 4000
|
||||
-1 0 0 1
|
||||
$EndComp
|
||||
Text GLabel 7800 4050 2 60 Input ~ 0
|
||||
5V
|
||||
$Comp
|
||||
L GND #PWR04
|
||||
L GND #PWR03
|
||||
U 1 1 59BCF11C
|
||||
P 8300 4000
|
||||
F 0 "#PWR04" H 8300 3750 50 0001 C CNN
|
||||
F 0 "#PWR03" H 8300 3750 50 0001 C CNN
|
||||
F 1 "GND" H 8300 3850 50 0000 C CNN
|
||||
F 2 "" H 8300 4000 50 0000 C CNN
|
||||
F 3 "" H 8300 4000 50 0000 C CNN
|
||||
1 8300 4000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
Text GLabel 8300 4000 2 60 Input ~ 0
|
||||
Ground
|
||||
Text GLabel 7150 4500 2 60 Input ~ 0
|
||||
5V
|
||||
Wire Wire Line
|
||||
7150 4500 7000 4500
|
||||
Wire Wire Line
|
||||
7000 4500 7000 4750
|
||||
Connection ~ 7000 4650
|
||||
Wire Wire Line
|
||||
7000 4650 7650 4650
|
||||
NoConn ~ 6500 4650
|
||||
NoConn ~ 6500 4750
|
||||
NoConn ~ 6500 4850
|
||||
NoConn ~ 6500 4950
|
||||
NoConn ~ 6500 5050
|
||||
$Comp
|
||||
L PWR_FLAG #FLG04
|
||||
U 1 1 59C3E871
|
||||
P 7900 4000
|
||||
F 0 "#FLG04" H 7900 4095 50 0001 C CNN
|
||||
F 1 "PWR_FLAG" H 7900 4180 50 0000 C CNN
|
||||
F 2 "" H 7900 4000 50 0000 C CNN
|
||||
F 3 "" H 7900 4000 50 0000 C CNN
|
||||
1 7900 4000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L PWR_FLAG #FLG05
|
||||
U 1 1 59C3E889
|
||||
P 8300 4000
|
||||
F 0 "#FLG05" H 8300 4095 50 0001 C CNN
|
||||
F 1 "PWR_FLAG" H 8300 4180 50 0000 C CNN
|
||||
F 2 "" H 8300 4000 50 0000 C CNN
|
||||
F 3 "" H 8300 4000 50 0000 C CNN
|
||||
1 8300 4000
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$Comp
|
||||
L +5V #PWR06
|
||||
U 1 1 59C3E8A7
|
||||
P 7000 4500
|
||||
F 0 "#PWR06" H 7000 4350 50 0001 C CNN
|
||||
F 1 "+5V" H 7000 4640 50 0000 C CNN
|
||||
F 2 "" H 7000 4500 50 0000 C CNN
|
||||
F 3 "" H 7000 4500 50 0000 C CNN
|
||||
1 7000 4500
|
||||
1 0 0 -1
|
||||
$EndComp
|
||||
$EndSCHEMATC
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
<export version="D">
|
||||
<design>
|
||||
<source>/home/arofarn/Make/Cameteo/Serial-SHIM/Serial-SHIM.sch</source>
|
||||
<date>sam. 16 sept. 2017 11:28:28 CEST</date>
|
||||
<date>jeu. 21 sept. 2017 18:27:42 CEST</date>
|
||||
<tool>Eeschema 4.0.2+dfsg1-stable</tool>
|
||||
<sheet number="1" name="/" tstamps="/">
|
||||
<title_block>
|
||||
|
|
@ -21,12 +21,14 @@
|
|||
<components>
|
||||
<comp ref="Serial1">
|
||||
<value>CONN_01X04</value>
|
||||
<footprint>Pin_Headers:Pin_Header_Straight_1x04</footprint>
|
||||
<libsource lib="conn" part="CONN_01X04"/>
|
||||
<sheetpath names="/" tstamps="/"/>
|
||||
<tstamp>59BCE9F7</tstamp>
|
||||
</comp>
|
||||
<comp ref="PI-GPIO1">
|
||||
<value>CONN_02X05</value>
|
||||
<footprint>Pin_Headers:Pin_Header_Straight_2x05</footprint>
|
||||
<libsource lib="conn" part="CONN_02X05"/>
|
||||
<sheetpath names="/" tstamps="/"/>
|
||||
<tstamp>59BCEAE4</tstamp>
|
||||
|
|
@ -84,37 +86,37 @@
|
|||
</library>
|
||||
</libraries>
|
||||
<nets>
|
||||
<net code="1" name="Ground">
|
||||
<node ref="PI-GPIO1" pin="9"/>
|
||||
<net code="1" name="Net-(PI-GPIO1-Pad10)">
|
||||
<node ref="Serial1" pin="4"/>
|
||||
<node ref="PI-GPIO1" pin="10"/>
|
||||
</net>
|
||||
<net code="2" name="SDA">
|
||||
<node ref="PI-GPIO1" pin="3"/>
|
||||
</net>
|
||||
<net code="3" name="SDC">
|
||||
<node ref="PI-GPIO1" pin="5"/>
|
||||
</net>
|
||||
<net code="4" name="GPCLK0">
|
||||
<node ref="PI-GPIO1" pin="7"/>
|
||||
</net>
|
||||
<net code="5" name="5V">
|
||||
<node ref="Serial1" pin="1"/>
|
||||
<net code="3" name="+5V">
|
||||
<node ref="PI-GPIO1" pin="4"/>
|
||||
<node ref="Serial1" pin="1"/>
|
||||
<node ref="PI-GPIO1" pin="2"/>
|
||||
</net>
|
||||
<net code="6" name="3_3V">
|
||||
<net code="4" name="Net-(PI-GPIO1-Pad1)">
|
||||
<node ref="PI-GPIO1" pin="1"/>
|
||||
</net>
|
||||
<net code="7" name="Net-(PI-GPIO1-Pad6)">
|
||||
<net code="5" name="Net-(PI-GPIO1-Pad3)">
|
||||
<node ref="PI-GPIO1" pin="3"/>
|
||||
</net>
|
||||
<net code="6" name="Net-(PI-GPIO1-Pad5)">
|
||||
<node ref="PI-GPIO1" pin="5"/>
|
||||
</net>
|
||||
<net code="7" name="Net-(PI-GPIO1-Pad7)">
|
||||
<node ref="PI-GPIO1" pin="7"/>
|
||||
</net>
|
||||
<net code="8" name="Net-(PI-GPIO1-Pad9)">
|
||||
<node ref="PI-GPIO1" pin="9"/>
|
||||
</net>
|
||||
<net code="9" name="Net-(PI-GPIO1-Pad6)">
|
||||
<node ref="Serial1" pin="2"/>
|
||||
<node ref="PI-GPIO1" pin="6"/>
|
||||
</net>
|
||||
<net code="8" name="Net-(PI-GPIO1-Pad8)">
|
||||
<net code="10" name="Net-(PI-GPIO1-Pad8)">
|
||||
<node ref="Serial1" pin="3"/>
|
||||
<node ref="PI-GPIO1" pin="8"/>
|
||||
</net>
|
||||
<net code="9" name="Net-(PI-GPIO1-Pad10)">
|
||||
<node ref="PI-GPIO1" pin="10"/>
|
||||
<node ref="Serial1" pin="4"/>
|
||||
</net>
|
||||
</nets>
|
||||
</export>
|
||||
|
|
|
|||
Loading…
Reference in New Issue